The continuing trend of scaling down integrated circuits has forced the semiconductor industry to consider new techniques for fabricating smaller components at sub-micron levels. With the industry moving towards processes for fabrication of smaller device geometries, isolation between devices becomes a very critical issue.
Several isolation methods are currently prevalent in the semiconductor industry. One method, LOCal Oxidation of Silicon (LOCOS) uses patterned silicon nitride as an oxidation inhibitor so that the silicon substrate will oxidize where the nitride is removed and not oxidize where the nitride is present. A main fabrication concern when using LOCOS is the encroachment of oxide under the nitride that causes the well known “bird's-beak” problem.
A second isolation method is deep trench isolation, where a single deep trench is etched into the silicon substrate and then filled with oxide. However, deep trenches have proven difficult to reliably manufacture over an entire wafer and the width of the trench is limited to the critical dimension of a given process.
The present invention develops a method to fabricate device isolation for sub-micron fabrication processes. In particular, the present invention provides a device isolation method for processes using a device geometry of 0.1 μm or smaller.